A microprocessor system (MPS) is a system that includes at least 1 microprocessor (MP), a storage device (SRAM), input/output devices (I/O), devices for connecting the system bus with input/output devices (controllers), and a system bus.
This system can be considered as an example of an electronic system that is designed to process input signals and produce output signals. It is possible to use analog signals, single digital signals, digital codes, or a sequence of digital codes as input and output signals. In this system, as in any digital system, input analog signals are converted into sequences of codes using analog-to-digital converters (ADCs), and output analog signals are formed from sequences of codes using digital analog converters (DACs). Information is processed and stored in digital form.
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Typical structures of microprocessor systems.
The type of MS structure is determined by the composition and organization of the memory and input/output subsystem (IO).
In memory you can highlight:
● read-only memory devices (ROM), used to store programs and constants;
● random access memory (RAM), designed to store variables and externally loaded object code (programs).
In the explosive subsystem, a number of complete functional modules can be distinguished:
● ports—the simplest modules in the form of buffer circuits and registers addressed by the central processing unit (CPU);
● peripheral adapters (PA) - more complex software-controlled modules. When using BB tools to control external devices, they are called peripheral controllers;
● BB coprocessors are the most complex modules that operate according to their own programs.
The main typical structures of MS include:
● backbone structure (Fig. 3.1.1, a), in which all modules are connected to the backbone. The use of a single backbone ensures the execution of one data exchange operation between two (in general, any) system modules in one work cycle;
● backbone-cascade (Fig. 3.1.1, b) and backbone-radial (Fig. 3.1.1, c) structures, which use bus controllers to implement priority relationships when accessing the backbone.
At any given time, the highway is made available to one functional module. In the simplest MSs, the role of the active module is performed by the central processor (CPU), which organizes the control of the highway. In more complex systems, the backbone is distributed among individual modules in accordance with requests for its capture and priority agreements. This task is assigned to the system backbone arbiter.
Highways of microprocessor systems.
The exchange of information between the central processing unit (CPU) and the memory and input/output (IO) subsystem occurs via an intra-system bus, which is a single set of system buses. The most commonly used is a three-bus bus with separate address and data buses. It consists of the following tires (Fig. 3.1.2, a):
● SD data bus, intended for data exchange;
● address bus ША, over which the addresses of memory cells or ports are transmitted during calls;
● control bus, which serves to control the operation of the system.
Some microprocessors (for example, MS S-51 microcontrollers) have a combined address/data bus (AS/D). A microsystem with a two-bus bus is shown in Fig. 3.1.2, b. In this case, to separate the functions of the combined SHA/D bus, an address reading strobe (RtA) is used. When PtA = 1, the ShA/D bus performs the address transfer function, and when PtA = 0, it performs the data transfer function. The address is usually fixed by a cut (the transition of the CHA from 1 to 0) in a special address register (Fig. 3.1.3, a, b).
Organization of memory and input/output spaces.
From a programmer's point of view, memory can be represented as an ordered set of 8-bit cells (Fig. 3.1.4, a). Each memory cell (byte) is associated with a number (number), called the cell address. The sequence of addresses is an integer series from 0 to 2 m – 1, where m is the width of the address code, determined by the number of lines of the address bus. The collection of all addresses forms the memory address space. Such a space and its address are called linear. In the 8-bit processors discussed above, the linear address is equivalent to the physical address, which is set on the address bus to access physical memory with a capacity of 216 = 64K bytes.
The linear address space provides access to any byte of memory (Fig. 3.1.4, b). Words (2 bytes) and double words (4 bytes) occupy adjacent bytes in linear memory. The order of the bytes inside a word is: first the least significant (L-byte), then the most significant (H-byte) byte of the word (Fig. 3.1.4, c, d). The L-byte address serves as the address of the entire word and can be either even or odd (by choosing the starting address An).
The memory address space can be divided into three components:
● CSEG (Code Segment) - memory space of commands (code, programs);
● DSEG (Data Segment) - data memory space;
● RSEG (Register Segment) - memory space of programmatically accessible registers.
The organization of command and data memory is influenced by the architecture of the MS. In systems with the Harvard architecture, the instruction and data memory spaces are separated. Systems with Princeton architecture have shared memory and a single address space for instructions and data. Note that with a segmented memory organization, separate access to command segments and data segments is implemented, but the segments themselves can be located at any address.
The RSEG space may be completely isolated from or overlap with the DSEG data space. RSEG shared space systems have systems that support fast access to all or at least some of the DSEG data memory. In such systems, individual processor registers are treated as ordinary data memory cells.
The input/output subsystem (IO) can be represented as an IOSEG space ( Input / Out Segment ) and access rules to it. There are two possible types of IOSEG spaces:
● isolated space IOSEG, which is represented by a set of n cells (ports), with random access to each of them. For most MSs, the port width is 8 or 16 bits. Like memory space, the space of memory is linearly ordered. Each IOSEG space element has its own address. The address range depends on the number m of address bits and has limits of 0 and 2 m –
1. For many processors, commands are provided for accessing ports, for example, IN input and OUT output;
● shared IOSEG space, for which areas in the DSEG data memory space are allocated for port addressing. As will be shown below, in this case the same organization of access to ports is used as to memory cells.
Organization of access to memory and input/output devices.
With a 16-bit CPU address bus, memory space is limited to addresses 0000...FFFFh in hexadecimal (h) notation, which corresponds to decimal memory location numbers 0 to 65535. The amount of memory required is determined by the type and number of selected memory chips used as memory modules.
To understand the principles of organizing memory access, let's look at an example. Let's assume that the MS memory capacity is 4K bytes. In this case, the memory contains one ROM module and 255 RAM modules with a capacity of 256 bytes each. The memory modules have eight address inputs A7.....A0, a crystal sampling input CS, read/write inputs and data outputs.
The memory access organization diagram for this case is shown in Fig. 3.1.5. To access memory, 12 address bus lines must be used. To select a cell in the memory module, the low-order bits of the address A7, A0 are allocated. The codes of the lower address bits are supplied to the address inputs of all modules simultaneously. The selection of the required kth memory module is made by applying a low-level signal ¯CS = 0 to the sampling input of the crystal. These signals are generated at the output of the DC decoder. The decoder inputs receive signals from the most significant bits of addresses A11.....A7. Reading from ROM and RAM and writing to RAM is initiated by a low level of the signals ¯ChtP and ¯ZpP. When the signal level is high, the memory modules are in a passive state. This allows you to use the address bus to organize access to I/O devices.
Right side of Fig. 3.1.5 illustrates the principle of organizing access to external devices - an input/output device (I/O), an input device (I/O) and an output device (I/O). For addressing devices, the low-order address bits A7, A0 are allocated. The operation of I/O and input devices is initiated by the application of the write signal ¯ЗпУВВ, and the operation of input/output and output devices by the application of the read signal ¯ТУВВ. 8-bit data operands and the readiness signal GT are removed from the device outputs (CAPTURE REQUEST, INTERRUPTION REQUEST signals, etc. are also possible). With 8-bit addressing, it is possible to connect 256 I/O devices or simultaneously 256 input devices and 256 output devices.
General understanding of microprocessors
To manage or control certain processes, appropriate software support on a real technical basis is required. This function is performed by one or a set of microcircuits on basic matrix crystals. For practical needs, chip-set modules are almost always used, that is, sets of chips that are connected by a common power system, signals, information processing formats, and so on. In a scientific interpretation, as noted in the theoretical foundations of microprocessor technology, such devices represent a place (main memory) for storing operands and instructions in encoded form. Direct control is implemented at a higher level, but also through microprocessor integrated circuits. Controllers are used for this.
We can talk about controllers only in relation to microcomputers or microcomputers consisting of microprocessors. Actually, this is working equipment, in principle capable of performing certain operations or commands within the framework of a given algorithm. As noted in the textbook on microprocessor technology by Liventsov S.N., a microcontroller should be understood as a computer focused on performing logical operations within the framework of equipment control. It is based on the same schemes, but with limited computing resources. The task of the microcontroller is largely to implement critical but simple procedures without complex circuits. However, such devices cannot be called technologically primitive either, since in modern production microcontrollers can simultaneously manage hundreds and even thousands of operations simultaneously, taking into account the indirect parameters of their execution. Overall, the logic structure of a microcontroller is designed for power, versatility, and reliability.
Cycles of access to the highway.
When exchanging data between the central processing unit (CPU) and memory or input/output subsystem (IO), one word or byte is transferred per cycle of access to the bus. There are several typical exchange cycles:
● cycles of reading memory and writing to memory;
● cycles of reading and writing to BB devices (ports) (with isolated BB IOSEG space);
● program memory read cycle (for Harvard-type architecture);
● memory read-write cycle (for a two-bus bus). This cycle, which requires a one-time address transfer, is used to increase the throughput of the backbone.
To control the cycles, various sets of signals (commands) are used, transmitted via the control bus. The signals are rectangular pulses and are called strobes. Below are two possible sets as an example.
1st set¯ChP memory reading (Memory Read Command - MRDC);
¯ChP write to memory (Memory Write Command - MWTC);
¯ChtUVV reading from the BB device Input/Output Read Command - IORC);
¯ZpUVV write to the explosive device (Input/Output Write Command - IOWC);
Read program memory (Program Segment Enable - PSEN).
2nd set ¯Thu reading RD ( Read );
¯Зп record WR ( Write );
П/¯УВВ choice of memory space or explosives (Memory or Input / Output - М/IO);
VPP selection of program memory (Code - COD).
It should be noted that with the help of logic circuits the second set can be converted into the first. Combined use of both sets is possible.
Time diagrams of access cycles to three-bus and two-bus lines are shown in Fig. 3.1.6, a, b.
To separate the functions of a combined S/D dual-bus bus, an address read strobe (RA) is used. The address is fixed by a cut (the transition of the CHA from 1 to 0) in a special address register (Fig. 3.1.3, a).
In the timing diagrams below:
● in the reading cycle:
• the address is set earlier and removed after the reading strobe ¯Thu;
• data is set and removed with a delay relative to the reading strobe ¯Thu;
• data is captured on the falling edge of the reading strobe ¯Th;
● in a recording cycle:
• address and data are set earlier and removed later than the recording strobe ¯Zp;
• data is true during the entire duration of the write strobe or is fixed at the falling edge of the write strobe ¯ЗпЗФ (for LSI with a dynamic synchronization input).
The ZpZF strobe improves the speed characteristics of the highway.
The considered cycles of access to the highway can be implemented when the microprocessor exchanges with high-speed peripheral devices of the control unit, such as, for example, memory. To organize reliable exchange with low-speed external devices, an additional control line is introduced, through which an exchange confirmation signal (EP) or readiness signal (RT) is transmitted.
With the classical organization of exchange (Fig. 3.1.7), an external device in the exchange state produces a signal POb = 1, otherwise - POb = 0. In each access cycle until the end of the read/write strobe ( ¯R = 0 or ¯ ZpZF = 0) The CPU checks (by the cutoff of the TI clock pulses) the state of the POb signal. If the test shows VPb = 0, the CPU goes into the confirmation wait state, generating the signal AOb = 1. After the exchange confirmation signal is established and the next test shows POb = 1, the CPU clears the confirmation wait signals (OzP = 0) and read/write ( ¯T / ¯ZpZF =1). Data is captured by a slice (from 0 to 1) of read/write signals. The external device confirms the completion of the exchange by resetting the exchange confirmation signal (EC).
Events are possible within the MS that require an immediate interruption of the main program and a transition to servicing another program, called a subroutine. The CPU's response to these events ends with a return to the main program. The moments of occurrence of such events are not known, and therefore cannot be taken into account when drawing up the main program. The process of servicing them must be carried out in parallel and hidden from the main program. Each program interrupt (exception) is preceded by a radial interrupt request signal (IRR k), which is generated by an external device (or CPU) and calls the interrupt service routine. Hardware and software that provide organization and maintenance of interrupts form an interrupt system. In the case when the event is caused by an external device, the CPU receives a vector request signal indicating the occurrence of one or more radial requests ZPr k, and proceeds to execute a special machine cycle - the interrupt vector input cycle. In this cycle, the information associated with the number k of the radial request is entered and the transition to the corresponding maintenance subroutine is carried out. The interrupt vector input cycle differs from the data input cycle in that it uses an interrupt acknowledge strobe (IA) instead of an I/O device read strobe (I/O device read strobe). When servicing interrupts, the main program interacts with the subroutine through data structures located in memory - interaction areas, reading and modifying data in these areas.
External interfaces
The microprocessor is rarely considered as an isolated system for executing single-syllable instructions in a static format. There are devices that process one signal according to a given scheme, but most often microprocessor technology works with a large number of communication connections from sources, which themselves are not linear in terms of the commands being processed. To organize interaction with third-party equipment and data sources, special connection formats are provided - interfaces. But first you need to determine what exactly the communication is being done with. As a rule, controlled devices act in this capacity, that is, they receive a command from the microprocessor, and in feedback mode they can receive data on the status of the executive body.
As for external interfaces, they serve not just to enable the interaction of a certain actuator, but also to integrate it into the structure of the control complex. In relation to complex computer and microprocessor technology, this can be a whole set of hardware and software closely related to the controller. Moreover, microcontrollers often combine the functions of processing and issuing commands with the tasks of providing communication between microprocessors and external devices.
Buffering of data and address buses.
The currents consumed by memory and I/O devices along the data and address bus circuits significantly exceed the permissible current values for processor chips. Therefore, these devices are connected to the data and address buses of the microprocessor through buffers, which are pulse amplifiers. Buffers often use elements with three output states, the two normal states corresponding to the high and low output levels, and the third Z state representing the high impedance output impedance of the element. In state Z, the element is practically disconnected from the load.
An element with a Z-state can be implemented, for example, by introducing a semiconductor diode VD 2 into a standard TTL inverter circuit (Fig. 3.1.8, a). If at the control input Z = 0, then the collector potential (as well as the emitter) of transistor VT 2 is close to zero and therefore the output transistors VT Z, VT 4 are in cutoff mode, i.e., in an open state. When Z = 1, diode VD 2 is turned off, and the TTL inverter with input X and output Y operates in normal mode. By connecting to the X input of the inverter, a repeater with three output states is obtained. In Fig. 3.1.8, b, c shows graphic symbols of a repeater and inverter with three output states.
To build data and address bus buffers, you can use bus shapers that allow controlled bidirectional transmission of 8-bit words. In Fig. 3.1.8d shows a diagram illustrating the principle of constructing a bus driver used in 8-bit processors. The kth transmission chain of the driver (k = 0, ..., 7) includes two repeaters P1, P2 with three possible output states. The states of the repeaters are controlled using logical elements LE1, LE2. The operating modes of the shaper are given in table. 3.1.1.
As can be seen from table. 3.1.1, the crystal sampling signal ¯ВК = 0 activates the transmission of information through repeaters, while the T signal determines the number of the active (on) repeater P1 or P2. When ¯ВК = 1 there is no information transfer, and the value of the signal T is indifferent. This fact is marked in the table with the symbol Ф (0 or 1). The Yk outputs have a greater load capacity than the Xk inputs, since memory and I/O devices are connected to them. When constructing devices based on 8-bit microprocessors, the bus driver itself is used as a data bus buffer, and the address bus buffer (16 lines) is made up of two such drivers by connecting pins ¯ВК and Т.
Device Manufacturers
At the origins of the creation of microprocessor devices were engineers from Intel, who released a whole line of 8-bit microcontrollers on the MCS-51 platform, which are still used in some areas today. Also, many other manufacturers used the x51 family for their own projects as part of the development of new generations of electronics and microprocessor technology, including domestic developments like the K1816BE51 single-chip computer.
Having entered the segment of more complex processors, Intel gave way to microcontrollers to other companies, including Analog Device and Atmel. A fundamentally new look at microprocessor architecture is offered by Zilog, Microchip, NEC, and others. Today, in the context of the development of microprocessor technology, the x51, AVR and PIC lines can be considered the most successful. If we talk about development trends, then today the requirements for expanding the range of internal control tasks, compactness and low power consumption come first. In other words, microcontrollers are becoming smaller and more efficient in terms of maintenance, but at the same time increasing their power potential.
